This invention relates to a superconducting digital demultiplexer (DEMUX) and, in particular, to a DEMUX employing Josephson junction technology.
In the discussion to follow, the invention will be illustrated using a particular type of Josephson junction technology denoted generally as rapid single-flux quantum (RSFQ) circuitry. The RSFQ circuitry is generally characterized by the use of "overdamped" Josephson junctions which have a single valued current-voltage (I-V) characteristic; i.e., they are non-hysteretic. This also implies that after a current pulse, which exceeds the critical current (Ic), the junction is self-reset to its original superconducting state.
There are many devices such as RSFQ analog-to-digital converters (ADCs) which generate digital data at such a fast rate that conventional semiconductor electronics can not process the data. It is known that by demultiplexing a "fast" data stream into several subsidiary data streams, the rate of the "fast" data stream is effectively slowed in the subsidiary streams. This can be done by distributing the bits of the original fast data stream, one at a time, to several slower digital channels (lines or circuits). By way of example, the "fast" data bits on an input channel can be distributed among N channels where the data rate on the N channels is 1/N times the rate of the input transmitting channel. An advantage of demultiplexing is that the circuits processing the slower data can be made using a slower, less expensive technology. The tradeoff is that more circuitry is required. However, a reduction in speed by a factor of N accompanied by a reduction in cost much greater than N, may result in significant economic advantage. Also, reducing the effective speed enables the data to be coupled to many different electronic circuits.
Although the idea of demultiplexing is known, actual circuits for demultiplexing the extremely high rate of the RSFQ generated data streams need to be developed. Because of the speed involved, it is desirable that the demultiplexers employ Josephson junctions (JJs). Also, in dealing with extremely high speed circuits, the delays in the transmission of signals from one part of the circuit to another, can lead to timing errors relative to some clock signal. Therefore a synchronous operation tied to some clock signal would tend to limit the maximum speed at which the circuit can be operated.
It is therefore an object of the present invention to have a self-synchronizing (asynchronous) demultiplexer which does not require a clock signal.
It is another object of the invention to have an extremely high speed demultiplexer employing Josephson junctions.
It is a still further object of the invention to have a demultiplexer whose sections can be easily cascaded to produce higher order demultiplexing.
It is a still further object of the invention to have a dual-rail (i.e., two input lines) demultiplexer in which information is transferred between circuits by means of two lines with one line carrying (transmitting) the "one" logic signals and the second line carrying (transmitting) the "zero" logic signals.